Metrics and bounds for phase delay and signal attenuation in RC(L) clock treesCELIK, M; PILEGGI, L. T.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 3, pp 293-300, issn 0278-0070Article

Simulation of lossy multiconductor transmission lines using backward Euler integrationCELIK, M; PILEGGI, L. T.IEEE transactions on circuits and systems. 1, Fundamental theory and applications. 1998, Vol 45, Num 3, pp 238-243, issn 1057-7122Article

Modeling lossy transmission lines using the method of characteristicsGUPTA, R; PILEGGI, L. T.IEEE transactions on circuits and systems. 1, Fundamental theory and applications. 1996, Vol 43, Num 7, pp 580-582, issn 1057-7122Article

Error bounds for capacitance extraction via window techniquesBEATTIE, M. W; PILEGGI, L. T.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 3, pp 311-321, issn 0278-0070Article

Moment-sensitivity-based wire sizing for skew reduction in on-chip clock netsPULLELA, S; MENEZES, N; PILEGGI, L. T et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1997, Vol 16, Num 2, pp 210-215, issn 0278-0070Article

Performance computation for precharacterized CMOS gates with RC loadsDARTU, F; MENEZES, N; PILEGGI, L. T et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1996, Vol 15, Num 5, pp 544-553, issn 0278-0070Article

A sequential quadratic programming approach to concurrent gate and wire sizingMENEZES, N; BALDICK, R; PILEGGI, L. T et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1997, Vol 16, Num 8, pp 867-881, issn 0278-0070Article

The Elmore delay as a bound for RC trees with generalized input signalsGUPTA, R; TUTUIANU, B; PILEGGI, L. T et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1997, Vol 16, Num 1, pp 95-104, issn 0278-0070Article

Transmission line synthesis via constrained multivariable optimizationGUPTA, R; KRAUTER, B; PILEGGI, L. T et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1997, Vol 16, Num 1, pp 6-19, issn 0278-0070Article

Post-processing of clock trees via wiresizing and buffering for robust designPULLELA, S; MENEZES, N; PILEGGI, L. T et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1996, Vol 15, Num 6, pp 691-701, issn 0278-0070Article

PRIMA: Passive reduced-order interconnect macromodeling algorithmODABASIOGLU, A; CELIK, M; PILEGGI, L. T et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 8, pp 645-654, issn 0278-0070Article

Domain characterization of transmission line models and analysesGUPTA, R; KIM, S.-Y; PILEGGI, L. T et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1996, Vol 15, Num 2, pp 184-193, issn 0278-0070Article

Low power design of off-chip drivers and transmission lines : A branch and bound approachGUPTA, R; WILLIS, J; PILEGGI, L. T et al.International journal of high speed electronics and systems. 1996, Vol 7, Num 2, pp 249-267Article

EWA : Efficient wiring-sizing algorithm for signal nets and clock netsKAY, R; PILEGGI, L. T.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 1, pp 40-49, issn 0278-0070Conference Paper